In the known art, as shown in FIG. 1, the structure of a known low temperature polysilicon thin film transistor (LTPS-TFT) is shown.
It is not difficult to obtain a method for fabricating the LTPS-TFT from the illustrated structure, which is described as follows.
A substrate layer, a SiNx layer, and a SiOx layer are sequentially deposited to form a substrate, and then an a-Si (amorphous silicon) layer is deposited. The a-Si layer is irradiated by laser to recrystallize the a-Si layer into a polysilicon film. A pattern layer structure can be then formed using a yellow light/etching process.
After that, N+ doped area and N− doped (lightly doped drain) area are defined in the pattern layer structure using two masks and corresponding yellow light photoresists, respectively. The N+ and N− doped areas are doped with different dosage of P31 (i.e., phosphorus having relative molecular weight of 31). That is, P31 is doped using an ion implantation process to obtain the N− area.
After multiple depositing processes, yellow light processes and etching processes, a gate insulator (silicon nitride), a gate electrode (GE), a source electrode and a drain electrode as shown in figure are formed.
It is not difficult to understand that the existing technique employees repeating depositing processes, yellow light processes and etching processes. The complexity of the process is increased, the manufacturing cost is high and the producing efficiency is relatively low.